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FC940L Low Voltage 1 to 18 Clock Distribution Device with Selectable PECL or LVTTL Input
August 1998 Revised January 1999
FC940L Low Voltage 1 to 18 Clock Distribution Device with Selectable PECL or LVTTL Input
General Description
The FC940L is a 1 to 18 low voltage clock fanout buffer. The device allows for the selection of either differential PECL or LVTTL/CMOS input levels. The 18 outputs are compatible with LVCMOS or LVTTL technology and are capable of driving 50 series or parallel terminated lines. The device has a minimal propagation delay and features low part-to-part and pin-to-pin skews. The outputs of the device are designed to operate at either 2.5V or 3.3V VCC. The output transistors have a 20 (30) impedance at 3.3V (2.5V) VCC. The input and core circuitry operate at 3.3V. The FC940L is fabricated in a high performance BiCMOS Process.
Features
s Selectable Differential PECL or LVTTL/CMOS inputs s 2.5V/3.3V output VCC supply operation s Typical propagation delays 2.5 ns s Part-to-Part skew < 900 ps s Typical Pin-to-Pin skew 200 ps s Ability to drive 50 series or parallel terminated transmission lines s Latchup performance exceeds 300 mA s ESD performance: Human body model > 2000V Machine model > 200V s Pin compatible to MPC940L s 32 pin TQFP package
Ordering Code:
Order Number FC940LVB Package Number VBE32A Package Description 32-Lead Thin Quad Flat Package, JEDEC MO-136, 7mm Square
Device also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignment for TQFP
Pin Descriptions
Pin Names PECL_CLK, PECL_CLK LVC_CLK SEL O[0:17] Description Differential PECL Input LVTTL/CMOS Clock Input Input Selection Pin Low Voltage CMOS Outputs
Truth Table
Inputs PECL_CLK L H X X
H = High Voltage Level L = Low Voltage Level X = Immaterial
Outputs SEL L L H H O0-O17 L H L H
LVC_CLK X X L H
(c) 1999 Fairchild Semiconductor Corporation
DS500140.prf
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FC940L
Functional Description
The FC940L is a 1 to 18 Clock distribution fanout buffer. The devices accept either a differential PECL or LVCMOS/ LVTTL input signal and generates 18 LVCMOS output signals. The SEL signal selects the differential PECL CLK input signals when held at a logic "L" and selects the LVCMOS CLK input signal when held at a logic "H". The complete functional operation is shown in the Truth Table. The output buffers support the ability to be powered by either a 2.5V or 3.3V VCC. The internal core voltage is required to be a 3.3V. The selectable input stage allows the device to be used in combination with either LVTTL/LVCMOS or LVPECL clock generation devices. The LVPECL inputs make this device ideal for use in large clock distribution systems where there are multiple levels of hierarchy.
Logic Diagram
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FC940L
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) (Note 2) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V VO > VCC DC Output Source/Sink Current (IO) DC VCC or Ground Current per Supply Pin (ICC or Ground) Storage Temperature Range (TSTG) Ambient Temperature Under Bias (TA) Case Temperature Under Bias (TC) 100 mA -65C to + 150C 0C to + 70C 0C to + 110C -50 mA +50 mA 50 mA -50 mA -0.5V to +4.6V -0.5V to +4.6V -0.5V to VCC + 0.5V
Recommended Operating Conditions
Power Supply Voltage (VCC) VCC I VCC O(Note 3) Input Voltage (VIN) Output Voltage (VO) Output Current in IOH/IOL VCC O = 3.135V to 3.465V VCC O = 2.375V to 2.625V Free Air Operating Temperature Input Edge Rate (t/V) VIN = 0.8V to 2.0V, VCC = 3.135V < 10 ns/V
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: Absolute Maximum Rating must be observed. Note 3: VCCO VCC1
3.135V to 3.465V 2.375 to 3.465V 0V to VCC 0V to VCC 24 mA 16 mA 0C to +70C
DC Electrical Characteristics (VCCI = 3.3 0.165V, VCCO = 3.3 0.165V)
Symbol VIH VIL VPP VCMR VOH VOL IIN ICC Parameter High Level Input Voltage Low Level Input Voltage Peak-to-Peak Input Voltage Common Mode Range (Note 4) High Level Output Voltage Low Level Output Voltage Input Current Quiescent Supply Current (ICCI + ICCO) PECL_CLK LVC_CLK All Outputs Low (ICCL) All Outputs High (ICCH) IOH = -100 A IOH = -24 mA IOL = 100 A IOL = 24 mA PECLK_CLK OTHER PECLK_CLK OTHER PECL_CLK Conditions VCCI TA = 0C to +70C VCCO Min 2.135 2.00 1.49 300 VCC-1.6 VCC-0.2 2.5 0.2 0.5 100 100 240 225 1.825 0.8 1000 VCC-0.8 Max 2.42 Units V V V V mV V V V V V A A mA mA
3.135-3.465 3.135-3.465 3.135-3.465 3.135-3.465 3.135-3.465 3.135-3.465 3.135-3.465 3.135-3.465 3.135-3.465 3.135-3.465 3.135-3.465 3.135-3.465 3.135-3.465 3.135-3.465 3.135 3.135 3.135 3.135 3.135-3.465 3.465 3.135-3.465 3.135-3.465 3.135-3.465 3.135-3.465 3.465 3.465 3.465 3.465
Note 4: VCMR is the difference between VCCI and the most positive side of the differential Input signal. Normal operation is obtained when the "high" input is within the VCMR Range and the inputs swing lies within the VPP specification. See figure 6.
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FC940L
DC Electrical Characteristics (VCCI = 3.3V 0.165V, VCCO = 2.5V 0.125V)
Symbol VIH VIL VPP VCMR VOH VOL IIN ICC Parameter High Level Input Voltage Low Level Input Voltage Peak-to-Peak Input Voltage Common Mode Range (Note 4) High Level Output Voltage Low Level Output Voltage Input Current Quiescent Supply Current (ICCI + ICCO) PECL_CLK LVC_CLK All Outputs Low (ICCL) All Outputs High (ICCH) IOH = -100 A IOH = -16 mA IOL = 100 A IOL = 16 mA PECLK_CLK OTHER PECLK_CLK OTHER Conditions VCCI VCCO TA = 0C to +70C Min 2.135 2.0 1.49 300 VCC-1.6 VCC-0.2 1.7 0.2 0.5 100 100 240 225 1.825 0.8 1000 VCC-0.8 Max 2.42 Units V V V V mV V V V V V A A mA mA
3.135-3.465 2.375-2.625 3.135-3.465 2.375-2.625 3.135-3.465 2.375-2.625 3.135-3.465 2.375-2.625 3.135-3.465 2.375-2.625 3.135-3.465 2.375-2.625 3.135-3.405 2.375-2.625 3.135 3.135 2.375 2.375 3.135-3.465 2.375-2.625 3.135-3.465 2.375-2.625 3.135-3.465 2.375-2.625 3.465 3.465 2.625 2.625
AC Electrical Characteristics (VCCI = 3.3V 0.165V, TA = 0C to +70C)
(Note 5)
Symbol fmax tPHL tPLH tPHL tPLH tr tf tOSLH tOSHL tSK(PR) tpwo Parameter Clock Frequency Propagation Delay PECL_CLK to On LVC_CLK to On Propagation Delay SEL to On Rise and Fall Time VCCO = 3.3V (0.8V to 2V) VCCO = 2.5V (0.7V to 1.6V) Pin-to-Pin Output Skew (Note 6) Part-to-Part Skew (Note 7) Output Pulse Width (Note 8) 45 900 55 45 900 55 ps % 200 600 600 200 ps ps 2.5 2.9 3.5 3.8 5.3 2.5 2.9 3.7 4.0 5.5 ns ns VCCO = 3.3V 0.165V Min 150 Typ Max VCCO = 2.5V 0.125V Min 150 Typ Max Units MHz
Note 5: AC Specifications are measured into a 50 Parallel terminated line. See Figure 1. Measurements are made with an input rise time of 1 ns/V. Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay between any two outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH tOSLH). Note 7: Part-to-Part Skew is defined as the variation in propagation delay between a specific output of device A and the same output of device B at the same VCC, temperature, output loading and input signal conditions. This specification is valid where all outputs of the device are tied together. This specification is guaranteed by design and statistical process distribution. Note 8: This specification assumes an input waveform with 50% duty cycle. The worst case duty cycle degradation will typically occur at fMAX.
Capacitance
TA = +25C Symbol CIN CPD Input Capacitance Power Dissipation Capacitance Parameter Conditions Typical VCC = Open, VI = 0V or VCC VI = 0V or VCC, f= 10 MHz, VCC = 3.3V 4 8 pF pF Units
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FC940L
AC Loading and Waveforms
FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Non-Inverting Output Signal
FIGURE 3. Waveform for Pin-to-Pin Output Skew
FIGURE 4. Duty Cycle Distortion dpwh=(tpwho-tpwhi); dpwl=(tpwlo-tpwli)
FIGURE 5. Output Pulse Width High/Low
FIGURE 6. Differential Input Signals Symbol PECL_CLK LVC_CLK VMI VCCI == 3.3V 0.165V 50% of Swing 1.5V VCCO = 3.3V 0.165V 1.5V 1.5V VMO VCCO = 2.5V 0.125V VCC/2 VCC/2
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FC940L Low Voltage 1 to 18 Clock Distribution Device with Selectable PECL or LVTTL Input
Physical Dimensions inches (millimeters) unless otherwise noted
32-Lead Thin Quad Flat Package, JEDEC, M0-136, 7mm Square Package Number VBE32A
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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